PLDs are a well-known type of integrated circuit that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to Input/Output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Part of the FPGA design methodology is to allocate one or more power supplies within the FPGA depending upon the requirements of the particular functional blocks that are incorporated within the FPGA. Some FPGA blocks, such as the BRAMs, are designed with transistors having relatively thin gate oxide layers for operation at a relatively low voltage level to minimize power consumption. In the I/O portions of the FPGA, on the other hand, a higher operational voltage is required because communication with devices external to the FPGA necessitates an extended dynamic range. Still other portions of the FPGA are designed for operation using multiple power supply magnitudes, thus requiring transistors exhibiting varying oxide thicknesses, depending upon voltage level.
A programmable interconnect tile is then used to interconnect the various blocks of the FPGA. N-type Metal Oxide Semiconductor (NMOS) transistors, for example, are typically used as passgates, whereby higher level signals incident at the gate terminal of the passgates cause relatively lower level signals to propagate from the drain to source, or from the source to drain, terminals.
In the prior art, the disparity between the VGG level signals and the VDD level signals is minimal, being separated, for example, by approximately 50 millivolts (mV). Allowing for a greater differential to exist between VGG and VDD would provide several advantages not currently realized by the prior art. Among these advantages includes, providing for an extended differential between the VGG and VDD voltage levels to allow for an improved propagation time through the interconnect tile.
Such a voltage differential, however, is generally not supported by the prior art and hence cannot support an improved propagation time. Large voltage differentials were supported in the early version PLDs, however, such a voltage differential cannot be supported by the modern deep sub-micron and sub-100 nanometer (nm) memory cell designs.